> -----Original Message-----
> From: cctalk-bounces_at_classiccmp.org
> [mailto:cctalk-bounces_at_classiccmp.org]On Behalf Of Jochen Kunz
> Sent: 13 May, 2004 18:19
> To: General Discussion: On-Topic and Off-Topic Posts
> Subject: Re: DEC RK07 drive interface specs wanted
>
>
> On Thu, 13 May 2004 07:07:10 -0700 (PDT)
> "Peter C. Wallace" <pcw_at_mesanet.com> wrote:
>
> > Well, a Spartan3 XC3S200 is about $16, has about 27K bytes of block
> > RAM that can be used as RAM or ROM, and you could fit at least a
> > couple of 100 MHz 16 bit CPUs inside plus whatever other hardware was
> > required.
> Interresting.
> But can I get a PowerPC CPU + FPU + SDRAM interface in that?
>
Xilinx has embedded PowerPCs inside Virtex-II FPGAs. SDRAM interface is
certailnly possible to arrange on that kind of FPGA, if you need. PCI is
certainly possible to achieve at a cost (money or blood, sweat & tears).
For more info go see the site below.
http://www.xilinx.com/ipcenter/processor_central/ultracontroller/index.htm
>
> An other interresting Question:
> Are there free developement tools for the FPGAs available?
Probably not for this one. Anything commercial and good enough to handle
these big FPGAs will cost you dearly. Without any detailed knowledge I
would guess you will end up at about 10 to 20 kUSD (or more) for a profes-
sional design kit (e.g. Synplify HDL synthesis, Xilinx ISE place & route,
ALDEC AHDL simulator, all these Win blech :) The more *IX you want the
more bucks you have to pour into it. I know about gEDA and Icarus
verilog, but have so far had no luck...
> I have no PeeCee and I refuse to tuch M$ Bloat+Bugware.
We are all admitted to have an opinion, no matter how unpractical... ;)
Good luck.
/Ulf A.
Received on Thu May 13 2004 - 12:57:02 BST