DEC RK07 drive interface specs wanted

From: Tony Duell <ard_at_p850ug1.demon.co.uk>
Date: Sun May 16 15:28:52 2004

> software. But maybe the tools they use are very different from yours.
> AFAIK they use some shematic capturing to design the FPGA, no VHDL or
> the like.

No, I was using schematic capture tools too, and a right pain they were.

I have many moans...

Theu would (obviously) delete unused sectiuon of the schematic. This made
a lot of sense in general (say you had a macro that emulated a 7483
full-adder but you only used 3 stages of it, the 4th stage would be
removed by the compiler. Great, you didn't want unused logic filling up
the chip). The problem came if you accidentally tied an enable line to
the wrong state [1], it would happily remove 90% of your logic _and not
warn you about it_. Then, nect day, when the compile had finished, you'd
find the result was useless. Yes, I should have been more careful, but
equally, computers are there to keep an eye on things.

[1] This was remarkably easy to do. There were macros for things like 8
input muxes that looked just like the TTL equivalent (74151), but had
active-high rather than active-low enables. Yes, you should read the
manuals, but in a complex design, it was easy to forget

More seriously is that it couldn't be trusted not to mangle the circuit.
It is not obvious to those who've never used FPGAs that the 'wires' are
nothing of the sort, they go through routing switches on the chip, each
of which adds a few ns delay. Now the problem comes when 2 signals go
through different numbers of switchs, you can end up with a clock edge
occuring before the data or something like that. I could find no way to
tell that darn software that signal A had to take at least as fast a path
as signal B or whatever. Hmmm....

-tony
Received on Sun May 16 2004 - 15:28:52 BST