Flash ADC selection, or other approach?

From: Tom Jennings <tomj_at_wps.com>
Date: Wed Oct 20 15:09:40 2004

On Wed, 20 Oct 2004, Peter C. Wallace wrote:

>
> For 1 Million samples per second you might be able to use one of our PCI FPGA
> I/O cards. Its just a target device so 1 million 32 bit readings per second is
> about the top speed but it could do the clock generation, syncronous sampling
> (say 5 channels x 6 bits per word) and have a small (1 K word or so) FIFO to
> allow for interrupts etc. I'm willing to donate a card (and make a simple FPGA
> config) if you like.

I'm a bit unclear on what this thing is... is there a URL I
could read on what this device does?

What I have as input are five "analog" signal sources, either
raw head signal (NRZ), or NRZ-state decoded 20-volt logic levels;
suitably level-shifted and bandpassed.



My plan so far is this:

* Take N reads of raw head data, first.
* Take N reads of derived "digital" data, second.

(Quickly, with the initial assumption that memory spin time is
degrading the media, until proven otherwise.)

Then offline, decode the digital data first. I know what they
are supposed to look like. The three timing tracks, S1 S2 S3,
generate the various machine states within each minor cycle
(word cycle), and with 128 sectors, there's a lot of redundancy
with which I could recreate bum sector timing. Sector address
is it's own track, a simple table. The clock track is simple.

If all that's good, then I know my NRZ data from the head is
good, and that I have sufficient data to recreate the timing
tracks if necessary, hell, I could do it with a PC parallel
port and drivers.

If it's bad, then I can examine the raw head NRZ data and
determine what the problem is and if it's fixable (low gain, bad
head, etc). There's spare heads and the tracks seem fairly wide.)
Received on Wed Oct 20 2004 - 15:09:40 BST