Replacements for ST-406/ST-512 drives

From: Eric Smith <eric_at_brouhaha.com>
Date: Mon Feb 7 20:16:17 2005

Dwight wrote:
> The only info that needs to be stored is the distance between
> rising edges of the pulse from the drive.

That's true. Only the rising edges are significant. Now I
understand your toggle flip-flop; it causes alternate intervals
to be 0 and 1 levels, simplifying sampling at lower bit rates.
But the pulse position still needs to be determined accurately,
so I think you still need a high sample rate.

I was planning to use a one-shot (possibly implemented digitally
by sampling at a higher rate but not retaining all the samples),
but now I'll give some thought to using the T flip-flop. Since I'm
using an FPGA I can do it either way easily.

> For that information, one only needs to store a binary info of
> short/long. At least this is true for MFM.

For ideal MFM, there are three lengths, depending on the number of
zero bits between a pair of one bits:

   11 - two one bits are represented as two pulses separated by
           one bit time (200 ns)

   101 - two pulses separated by two bits times (400 ns)

   1001 - two consecutive zero bits have an extra clock pulse in
           the middle, so this pattern has three transitions with
           300 ns between each pair

   10001 - longer sequences of zeros have the clock bits between
           each pair of consecutive zeros, so this pattern has
           transition intervals of 300 ns, 200 ns, then 300 ns.

However, there are also coding violations used for the address and
data marks. These have a longer interval due to a missing clock
transition, so 400 ns needs to be encoded as well.

If the controller is writing with precompensation, that could
change the timings enough that a low-rate sampling scheme would
fail.

> I've not looked into RLL but suspect that it is also similar.

Instead of having four different timings between pulses, it has
more, at finer increments. This is where low-rate sampling
completely falls apart, especially with precomp.

For (2,7) RLL, the legal intervals are 200, 266, 333, 400, 466, and
533 ns.

I'm not sure if (1,7) RLL was used on drives with the ST506/ST412
interface, but it would have tighter requirements.

> The sampling frequency only needs to
> be fast enough to detect the difference between a short or
> long time between rising edges.

Needs to discriminate at least three intervals, as described above,
and more for RLL.

> It doesn't need to know anything about the pulse width,

True.

> which requires at least a 4X-5X increase in the sample rate.

That increase is needed regardless of whether you're actually
sampling the width, in order to get the pulse position accuracy
that is desired.

The 3.825 GB figure I quoted was for storing the raw channel samples
for an XT2190 (150/225 MB formatted capacity for MFM/RLL). Another
approach is to store only the delta times. If you store delta times
in units of 16.6 ns (60 MHz sampling, which might be just barely good
enough for RLL with precomp), you'd need seven bits per sample. At most
there will be 83.3K flux transitions per track, so you'd need 1.1 GB of
storage. It's not clear that this is enough reduction to warrant the
increase in circuit complexity.

Eric
Received on Mon Feb 07 2005 - 20:16:17 GMT