FPGAs and PDP-11's

From: allisonp_at_world.std.com <(allisonp_at_world.std.com)>
Date: Fri Aug 27 07:27:20 1999

> logic gates you can use it as RAM. The XC4010 has "400" CLBs (Complex Logic
> blocks) and each logic block is capable of implementing a 4 x 16 (16
> nybble) synchronous dual-port register file. So four CLBs give you 16 16
> bit registers to play with with 396 CLBs left over.

The routing will kill you faster than you think. Though they are pretty
neat parts.
> To Tonys comment about speed, yes the 50Mhz number is deceptive in that
> logic delays will make the effective speed slower. Several references have
> placed the "effective" speed at 1/3 to 1/2 the FPGA's speed (or in this
> case 16 - 25 Mhz) however for a bit more money, you can get a 200Mhz
> version of the same part.

Doing actual project with 3030-50 parts 10mhz was pretty good for a sync
counter as a reliable figure though some would do as much as 16mhz.
Memory based parts like that have fairly high rounting node delays.
the payboac ofcourse is programability.

> There is a very nice evaluation board for this part available from
> http://www.xess.com/FPGA/ that I've got and will be using in my first tests.

How many $$$ ?
> I did a preliminary "floor plan" for the PDP-8 and it used just under 1/3
> of the 4010 (or 75% of a 4005 given the routing issues, which leaves enough
> to do an M8660 serial port.)

Me I'd do a stretch-8 for fun. though yours sounds interesting too.

Received on Fri Aug 27 1999 - 07:27:20 BST

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