PDP era and a question

From: allisonp_at_world.std.com <(allisonp_at_world.std.com)>
Date: Fri Aug 27 07:36:24 1999

> The technology in FPGA's these days is such that it enables devices to
> operate between 10 and 50 times the speed of the old TTL logic designed in

Old ttl was nowhere near that much slower. The lowly 7400 in 72 was
comfortablly under 15ns, true the FPA part may be under 1ns now but...
that's not 50X! Of course adding interconnection delays and other factors
the 10x number is very honest.

> the '70's. That doesn't mean you can take a '70's design and
> "transliterate" it and make it run lots faster, though that is conceivable.

This is true of any from one logic system to another. PDP-8 for example
used a lot of "wired or" and similar logic in the data paths to conserve
gates. Of course that was a slower way to do it but lower cost too.
So a design translation can buy speed at the cost of logic or design
effort.

> Schematic entry would be the easiest way to clone the prints, but HDL is
> considered by many to be the best way to implement an architecture, the
> behavior of which is well defined and understood. If you build your device
> in VHDL or VERILOG, it is inherently portable, since both XILINX and Altera,
> among others, support both.

VHDL is the way to go but developing the description would be the real
work.

> access to the resources to implement it in a product they sell, provided you
> buy the parts from them. They cost a few dollars in small quantity, but if
> you say the right "things" when approaching them, and seem sufficiently
> eccentric, they'll treat you right.

Roger that. Besides, they know if you do one your likely to use it for
other things (drag factor).

Allison
Received on Fri Aug 27 1999 - 07:36:24 BST