Thanks for posting this information. It might be useful, in addition, at
least to me, to have to correspondence with the S-100 bus pins so they can
be cross-referenced to the '696 standard signal names. I do hve the 8080
data in house, but nothing tying it to the S-100 bus pinout or timing.
Actually, it might be as correct to say that 8088 signal names are more or
less like "all the other" microcomputers in the non-Motorola camp. with the
8085 and z-80, it became obvious that the large number of strange signals
generated by the 8080 didn't even help the Intel folks with the task of
interfacing the processor to memory and peripheral devices. The simple
interface used by the 8085 and Z-80, which had to be painstakingly created
from an 8080, lives on, in the ISA and other bus architectures. What it's
come down to over the last 20 years is that you need a pair of signals, i.e.
nRD and nWR to tell you (1) that something's going on, and (2) whether it's
a transfer of data to or from the processor. Additionally, it's nice to
know whether the read or write is between the processor and memory or I/O.
With the MOT class of processor, you have an address strobe to tell you a
cycle's begun, and you have to decode the address to determine whether it's
I/O space or memory that's the target. In either case, you need only one
level of logic to create the necessary strobes, and none of it is clocked
logic, so no nonessential time loss is generated.
One of the reasons the S-100 required such fast memory for its relatively
slow processors was that you had to operate relatively complex timing
structures to create proper timing. That's a reason the standard, in my
considered opinion, killed the S-100 rather than perpetuating it. Intel
figured this stuff out a decade earlier with its Multibus-I. That used a
very ISA-like set of bus handshakes. Because the '696 standards committee
couldn't take the hint from the rest of the world and simply pick WHICH
write signal to use and WHICH read signal to use and that they couldn't
figure out that the system didn't need to have data valid at the beginning
of a write cycle, but only a short while before the end, and that data had
to be held for a time after the end of a cycle, simply was a dreadful shame.
That's what happens when folks meet with no intention of compromising. The
result of course, was the chaos that results when surplus vendors e.g.
CompuPro/Godbout (cited here because they were BIG, not because they were
BAD) design their boards considering only what's out in the dozen 55-gal
drums full of TTL parts in the warehouse as opposed to how the functions can
be implemented BEST.
Dick
-----Original Message-----
From: Tony Duell <ard_at_p850ug1.demon.co.uk>
To: Discussion re-collecting of classic computers
<classiccmp_at_u.washington.edu>
Date: Monday, March 29, 1999 2:18 PM
Subject: Re: Rebirth of IMSAI
>>
>> GAWD! The 8080 data sheet! I wonder if my archives go back that far . .
.
>
>
>I know I still have the 8080 data sheet (actually a NatSemi version of
>it). I found it the other day when looking for the SC/MP data (which I
>also found...)
>
>> Soooo . . . the signals were named the same also, eh? pSYNC, /pWR,
sMEMR,
>> etc???
>
>I have the Imsai 8080 CPU board schematics here.
>
>Here are the signals (modulo buffering/inverting):
>
>reset/ -> 8224 clock generator reset
>Prdy, Xrdy logically ORed and fed to 8224 rdyin
>PINT/ -> 8080 INT
>HOLD/ latched by D-type (clocked from phi2), -> 8080 Hold
>POC <- 8224 reset output
>Phi1 <- levelshifted 8224 phi1 output
>SSW DIS/ -> logic -> data buffer enable pins
>Phi2 <- 8224 phi2ttl output
>Cloc <- gate-delayed version of phi2
>Data, address lines <- 8080
>Pwait, Pwr/, Pdbin, Pinte, Phlda, Psync <- 8080
>CCDSBL -> enable line on buffers for last list of signals.
>Addr disbl/ ditto for address buffers
>DO Disbl/ ditto for data out buffers
>RUN, SS -> logic -> data buffer control
>SINTA, SWO, SSTACK, SHLTA, SOUT, SM1, SINP, SMEMR <- 8212 latch on CPU
>data lines, clocked by STSTB from 8224.
>STAT DISBL -> enable of buffers for those lines.
>
>That#'s basically it. The S100 bus is very similar to the raw 8080 lines
>(like 8-bit ISA is pretty much 8088 signals).
>
>-tony
>
Received on Mon Mar 29 1999 - 15:53:38 BST