Speaking of 11/73s

From: Megan <mbg_at_world.std.com>
Date: Thu Sep 2 20:07:40 1999

>If you place the PMI memory under the CPU, it still works as normal Qbus
>memory. Someone (either Allison or Megan Gentry) once explained how PMI
>memory works, but I forget. I have never tried to use one board above
>and one board below - has anyone ever done so?

It uses the Qbus *and* the CD interconnect... when an address is placed
on the bus which falls in the memory space, the board responds with
the addressed word over the Qbus, and the adjacent word (longword
aligned) over the CD interconnect and it goes into the cache. So
for straight-line code, you can get almost 50% cache hit rate.

>The increase in speed is purely a hardware function and does not depend
>on the OS or anything else, although I have seen RT-11 able to "know"
>that PMI memory is or is not present - have not ever bothered to find
>out how.

Having written the code in RESORC which reports it, I can tell you...
The code first flushes the cache, then executes a bunch of NOPs. It
then checks the cache hit-miss register. If it is non-zero, then there
were cache hits, and thus there is PMI present (of course, it previously
had to determine that the machine was a KDJ-based machine).

Interestingly, the DCJ11 microcode is optimized for cache usage, and
if on a PRO380 one disables the cache, the performance drops through
the floor -- to about 11/23 performance...

                                        Megan Gentry
                                        Former RT-11 Developer

| Megan Gentry, EMT/B, PP-ASEL | Internet (work): gentry!zk3.dec.com |
| Unix Support Engineering Group | (home): mbg!world.std.com |
| Compaq Computer Corporation | addresses need '_at_' in place of '!' |
| 110 Spitbrook Rd. ZK03-2/T43 | URL: http://world.std.com/~mbg/ |
| Nashua, NH 03062 | "pdp-11 programmer - some assembler |
| (603) 884 1055 | required." - mbg |
Received on Thu Sep 02 1999 - 20:07:40 BST

This archive was generated by hypermail 2.3.0 : Fri Oct 10 2014 - 23:32:35 BST