CPU design at the gate level

From: Ben Franchuk <bfranchuk_at_jetnet.ab.ca>
Date: Wed Oct 31 12:39:28 2001

Chuck McManis wrote:
> At 08:15 AM 10/31/01, Ben wrote:
> >That is true there is baggage.My two gripes today are
> >
> >1) No bootstrapping a minimal system in hardware & software - you need
> >everything to run.
> Take a page from Classic computers as I did and put a dedicated "console
> processor" on the front of your FPGA.
Classic Computers??? From where? I am still grumbling that I could not
front panel interface on my fpga. I refuse to have a CPU to boot my CPU.
(Note hidden cpu's in HD's count too.) I want to hit reset and have the
CPU load from bootstrap device regardless of main memory. This is the
way I
have the FPGA set up, boot strap from the serial port.In fact if I had a
PROM bootstrap I would have not worked with my system as wire was broke
in the
middle between the FPGA and memory, and took forever to debug as a data
bit would float.

>I've got a board for doing a "soft"
> robot CPU that I hope to get to after BattleBots that has a PIC chip (small
> single chip MCU) as the console processor. It loads the main CPU from
> either serial EEPROM or from a serial line into the FPGA on power up,
> sequences the power, and provides the diagnostic interface when things go
> strangely.

Why use a eprom and counter when you can use 50 million transistors.:)
Only after the fpga works 100% will I burn a prom, as the PC --> FPGA is
good way to test the system.

Ben Franchuk.
BTW the prom for the FPGA is 512k bits or 64KB. I have a whopping 32K of
memory and will use 8k for a OS leaving 24k for programs. Some how a
FPGA config prom bigger than my basic system hints how big is normal
for everything.
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.
Received on Wed Oct 31 2001 - 12:39:28 GMT

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