CPU design at the gate level

From: Ben Franchuk <bfranchuk_at_jetnet.ab.ca>
Date: Wed Oct 31 14:30:02 2001

Chuck McManis wrote:

> The VAX series has had PDP-11 front ends that load microcode, run
> diagnostics, power cycle the system and boot the operating system. The
> D-series of machines from Xerox had microcode that was loaded from floppy,
> the IBM 360 machines did an initial microprogram load from floppy, the DEC
> 10 series had a PDP-11/40 as its console server, there are others. Its a
> tried and true technology.

I knew most of that, I thought you had a specific web page you got your
material
from
  

> This question doesn't make sense, if you want a front panel design it in,
> if you're talking about actually manipulating the bits in the FPGA then use
> another FPGA to make a JTAG front panel.

I was referring to the CPU design and Instruction Set. A hard reset
causes a
bootstrap program to read in off the serial port. I configure the FPGA
from a
host PC. The cpu is a 12/24 bit design.

Bootstrap format:
oooo, octal data
oooooooo] octal address load
oooooooo\ octal program start
<cr><lf> leader/white space
                
 
 
> Perhaps we're quibbling semantics. The role of the PIC in my design is as a
> serial port, and it has the ability to program serial EEPROMs so I don't
> need a special cable to reload the FPGA data, I just power cycle with a
> jumper set.

A handy feature.

> I guess you lost me here. You're saying that the FPGA configuration PROM
> was disconnected from the FPGA and that was hard to debug and so having an
> 8 pin PIC chip on board to run diagnostics for you in this sort of case is
> worthless and antithetical to your design goals?

You still have to program the PIC. The fault was with the general memory
bus,
not the FPGA configuration.
 
 In my case I actually needed the ability to add op-codes and
peripherals on
> the fly so I don't use PROM. In the mean time I down load new EEPROM
> configs on the fly and reset and go, easy to debug and can be shipped as
> final hardware as well.
Fancy stuff there.

> How is this any different than a PDP-11 where the microcode store might
> have more bits than main memory? Its one 8 pin part to hold the
> configuration information and one 8 pin part to control it.

I used a PDP-8/e and a PDP-S all in one BOX computers. :)
It is hard to get use to several meg of bits in a 8 bit package when you
still
remember using core memory.
Ben Franchuk.
-- 
Standard Disclaimer : 97% speculation 2% bad grammar 1% facts.
"Pre-historic Cpu's" http://www.jetnet.ab.ca/users/bfranchuk
Now with schematics.
Received on Wed Oct 31 2001 - 14:30:02 GMT

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