CPU design at the gate level

From: Richard Erlacher <edick_at_idcomm.com>
Date: Sat Sep 22 10:01:28 2001

What's unfortunate, at least from where I sit, is that though some sources give
you a schematic or an HDL of a CPU, yet they don't tell you WHY the choices made
in its design were made. Normally such decisions are normally driven by
requirements, be it for performance, or for specific addressing modes, chip
size, or whatever. It seems we never see light shed on such matters.

One caution is certainly warranted, however. Fully synchronous design became
the default method of designing circuits of anysubstance in the mid-late '80's.
One result, of course, was that signal races were easily avoided, and, with the
use of pipelining, it allowed for the acceleration of some processes at the cost
of increased latency. The use of fully sunchronous design drove up CPU cost,
however, and was not an automatically assumed strategy in the early '70's, so
you've got to consider WHEN a design was specified before making any assumptions
about why things were done in a given way.

Classic CPU's were mostly NOT fully synchronous, as fully synchronous design
required the use of costlier faster logic families throughout a design when that
wasn't necessarily warranted. Today's FPGA and CPLD devices, when used to host
a classic CPU design, eliminate the justifications for asynchronous design
strategies that were popular in the early '70's - late '80's. Their use
essentially requires the design be synchronous, not only because signal
distribution/routing resources are limited, but because propagation delays are
so different from wht they were in the original discrete version.

Anybody wishing to go through the process of CPU design, which, BTW, is a
required course in most EE curricula, needs to complete a thorough requirements
analysis just to put some firm limits on what the end-product has got to be.

Dick

----- Original Message -----
From: "Tom Uban" <uban_at_ubanproductions.com>
To: <classiccmp_at_classiccmp.org>
Sent: Saturday, September 22, 2001 8:12 AM
Subject: Re: CPU design at the gate level


> At 02:35 AM 9/22/01 +0100, you wrote:
> >>
> >> The book: "Computer Organization & Design, The Hardware/Software
> Interface",
> >> by David A. Patterson and John L. Hennessy is a pretty thorough modern
> book.
> >
> >Yes, unfortunately it is a 'modern book'. I read some of Hennessy and
> >Patterson once, and found it was great at telling me how to analyse a
> >processor design, and optimise it, and things like that, but it didn't
> >really tell me how to do the design in the first place.
> >
> >It seems to have been written for the modern 'engineer' -- the sort that
> >couldn't design an engine (in the original meaning of 'ingenious
> >mechanism') if his life depended on it. And as you might have guessed by
> >now, I have little time for 'engineers' who can't design and build
> >examples of the things they claim to understand.
> >
> >You couldn't take that book and learn enough to start wiring up gates and
> >flip-flops to make a processor :-(
>
> I beg to differ. I feel that the book does a fairly good job of covering
> all aspects of processor design to date. It does in fact describe how the
> ALU is implemented along with the data paths necessary to feed it. It
> also importantly covers the hows and whys of the control plane needed to
> make the data path function. The book teaches all of the various arithmetic
> concepts (like floating point) which are now expected in modern designs.
> With these more basic concepts, it also covers the hows and whys of
> performance.
>
> While it does not teach you how to use a wire wrap tool, it does cover
> basic logic design concepts (in an appendix) as well. Perhaps in your
> case it just has too many references to the popular processors of the
> day for your taste. But, just because they are popular today, does not
> mean that they cannot be powerful learning tools, even for those who
> are interested in the processors of yesteryear...
>
> What it does not do is give you a schematic of a processor and hold your
> hand while describing each gate. If this is what you want, then perhaps
> the set of (KB11-A central processor unit maintenance manual, PDP-11/45
> and PDP-11/50 system maintenance manual, and 11/45-0 engineering drawings)
> would be a better instructional set.
>
> Let's face it. No one book is going to teach someone everything that they
> need to know to be able to design the next "great" processor. There is
> also nothing better to teach a subject than to learn from what others
> have done in the past.
>
> --tom
>
>
Received on Sat Sep 22 2001 - 10:01:28 BST