>Classic CPU's were mostly NOT fully synchronous, as fully synchronous design
>required the use of costlier faster logic families throughout a
>design when that
>wasn't necessarily warranted. Today's FPGA and CPLD devices, when
>used to host
>a classic CPU design, eliminate the justifications for asynchronous design
>strategies that were popular in the early '70's - late '80's. Their use
>essentially requires the design be synchronous, not only because signal
>distribution/routing resources are limited, but because propagation delays are
>so different from wht they were in the original discrete version.
There's currently talk on the FLEX email list of implementing
a new CPU in an FPGA or CPLD for use in existing SS-30/SS-50 bus
systems in conjunction with things such as Michael Holley's new
floppy controller, as well as reducing the overall board count needed
for a complete system, including I/O and RAM, down to two.
Jeff
--
Home of the TRS-80 Model 2000 FAQ File
http://www.cchaven.com
http://www.geocities.com/siliconvalley/lakes/6757
Received on Sat Sep 22 2001 - 13:15:09 BST