CPU design at the gate level

From: Derek Peschel <dpeschel_at_eskimo.com>
Date: Sat Sep 22 14:40:58 2001

On Sat, Sep 22, 2001 at 09:01:28AM -0600, Richard Erlacher wrote:

> One caution is certainly warranted, however. Fully synchronous design became
> the default method of designing circuits of anysubstance in the mid-late '80's.

The pendulum may be swinging back toward asynchronous design.


The ACM article mentions the increased speed of asynchronous designs. As
you said, they are hard to analyze (and keep running); the article turns
that into an advantage by pointing out that hackers can't analyze them
easily either. :)

I don't necessarily buy the reasoning (these articles are pretty
superficial) but the point still bears thinking about.

-- Derek
Received on Sat Sep 22 2001 - 14:40:58 BST

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