CPU design at the gate level

From: Derek Peschel <dpeschel_at_eskimo.com>
Date: Sat Sep 22 14:40:58 2001

On Sat, Sep 22, 2001 at 09:01:28AM -0600, Richard Erlacher wrote:

> One caution is certainly warranted, however. Fully synchronous design became
> the default method of designing circuits of anysubstance in the mid-late '80's.

The pendulum may be swinging back toward asynchronous design.

http://www.acm.org/technews/articles/2001-3/0921f.html#item13

The ACM article mentions the increased speed of asynchronous designs. As
you said, they are hard to analyze (and keep running); the article turns
that into an advantage by pointing out that hackers can't analyze them
easily either. :)

I don't necessarily buy the reasoning (these articles are pretty
superficial) but the point still bears thinking about.

-- Derek
Received on Sat Sep 22 2001 - 14:40:58 BST

This archive was generated by hypermail 2.3.0 : Fri Oct 10 2014 - 23:34:26 BST