Assembly on a Apple IIc+

From: Hans Franke <>
Date: Mon Feb 10 13:27:01 2003

> > So perhaps "one instruction per clock cycle" may be awfully close
> > with pipelining and with use of zero page.

> You must be thinking of some different 6502 to the rest of us :-) As
> Sellam said, no 6502 opcode takes less than two clock cycles to
> execute, and most take more (up to 7): the only 2-cycle instructions
> are the ones with implied addressing, like RTS, CLI, TAX, ... This is
> why a 6502 running typical well-written code, running on a 2MHz clock,
> manages at best around 0.7 MIPS.

> There's no pipelining at all in a 6502. No overlap of instructions
> whatsoever.

Beg your pardon, but that's not completle true. For basic
instructions timeing the timeing is always equivalent to
the number of memory accesses. So a LDA zp has 3 cylces,
two for the instruction and one for the data byte.

The excepton here are
a) One byte (inpled/accumulator) instructions, which always
   take two cycles
b) page misses, where the effective address crosses a page
c) RMW which add 2 cycles
d) taken braches which add 1 cycle.

Point d) alone gives a heavy hint about a pipelineing...

The 6502 pipeline can be seen as one byte deep.


VCF Europa 4.0 am 03./04. Mai 2003 in Muenchen
Received on Mon Feb 10 2003 - 13:27:01 GMT

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