a classiccmp electronics project?

From: Tom Jennings <tomj_at_wps.com>
Date: Sun Aug 1 16:18:58 2004

On Thu, 2004-07-29 at 17:05, Dwight K. Elvey wrote:

> Most of the applications Jay is talking about require faster
> than 100ns someplace. Most EPROMs just are not in that range.

How about: a fast RAM, with a PIC (and optionally E/EPROM) on the
backside. Upon reset, the PIC owns the RAM chip(s); it loads the RAM
with data from the EPROM/EEPROM, or serial line to a peecee, flips
control of the RAM interface to the "ROM" socket, and goes to sleep.

A cute trick commonly used in the CP/M days (and later) was to put a
boot EPROM board in the same (conflicting) memory space with RAM; the
EPROM code would proceed to "block copy" itself in place (read: EPROM;
write: RAM) then reset a flipflop that enabled the EPROM board.

EPROM board read access generated many wait states; the trick was the
EPROM board ignored write cycles but the underlying RAM didn't. I forget
how we handled the EPROM 'read' cycle but it was buss-safe (S100) and
Received on Sun Aug 01 2004 - 16:18:58 BST

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