q about PDP11/34 schematics (clock generation)

From: Bert Thomas <bert_at_brothom.nl>
Date: Sun Dec 26 16:49:21 2004

Tony Duell wrote:
> A delay line is what the name implies. A component that delays a signal,
> here a digital signal. If the input changes, then the output changes a
> certain time (here 150ns) later.

How precise is it? Is it comparable to a crystal oscillator regarding
stability and accuracy?

> The reason for multiple outputs (often called 'taps' is that you can get
> signals delayed by different amounts. A 150ns delay line may have 5 taps,
> say, 30ns apart. If the input changes, the first tap changes after
> 30ns,the next after 60ns, etc.

Are these typically linear distributed? I mean: are the time differences
between the taps always the same?

Thanks for your explaination Tony!

Received on Sun Dec 26 2004 - 16:49:21 GMT

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