HDL vs. schematics (was Re: ebay - cardamatic)

From: Eric Smith <eric_at_brouhaha.com>
Date: Wed Feb 16 11:11:02 2005

I wrote:
> Huh? Both VHDL and Verilog let you easily declare an adder.
> In VHDL, if you want an adder with inputs A and B, and output C,
> you would write:
[later correction:]
> C <= A + B;

woodelf wrote:
> Now what about carry out?

Since I declared C to be one bit wider than A and B, the most
significant bit of C is the carry out.

> 1's comp adder? Ripple adder or carry skip
> adder or carry lookahead adder? Where is over flow?

Well, if you specify the requirements poorly, you get a result that
doesn't meet them. You can do all those things in VHDL, but they
don't just happen automatically. Since they don't happen automatically
in a schematic either, I don't see the problem.

A schematic entry system might have predefined components for different
kinds of adders, but HDL synthesis system also provide predefined
components, so there's no obvious benefit either way.

I needed a carry lookahead adder for a 512-macrocell CPLD a while back,
so I wrote one in VHDL. Took about half an hour to write the adder,
a test bench, and simulate it. It would have taken me much longer to
draw a schematic of one (even using some predefined components) and a
set of test vectors.

Normally for FPGA design, ripply carry is perferred, because there
is a very fast hardware carry chain in the FPGA. Using carry lookahead,
carry skip, carry save, and other such techniques actually results in
a much slower adder. But if you're doing an ASIC design, the tradeoffs
are different. Good ASIC synthesis tools let you choose what kind of
adder will be generated, but for FPGAs there is no point.

Ones complement is used so rarely that normally it is explicitly
indicated with carry feedback, whether you're using schematics or an
HDL.

> But one nice thing about some schematic software I was using you can
> Zooom in on a component.

One nice thing about VHDL is that I don't have to zoom in and out.
Any reasonably sized VHDL module fits just fine in my emacs window.

Also it is much easier to "grep" HDL code. I spent an hour yesterday
trying to find an obscure signal on a twelve page schematic; if it
had been VHDL I would have found it in ten seconds.

> I have used FPGA's and found CPLD's to be the 'right size'.

CPLDs are the "right size" for some things, and not for others.
That's obvious, or there wouldn't be a market for FPGAs.

But I find VHDL to work great for CPLD design as well.

In the US, Verilog seems to be more popular than VHDL. However, I
prefer VHDL as it is much more expressive. Though "System Verilog"
has apparently filled in some of the gaps.

Eric
Received on Wed Feb 16 2005 - 11:11:02 GMT