HDL vs. schematics (was Re: ebay - cardamatic)

From: woodelf <bfranchuk_at_jetnet.ab.ca>
Date: Wed Feb 16 10:36:20 2005

Eric Smith wrote:

>woodelf wrote:
>> From what little I have seen FPGA's 99% is VHDL and VERLOG
>>for development. At least with a schematic you could trace out the
>>logic, I can't make hide nor hair of what the logic is with the
>>high level logic and you STIIL have to write code at the bit level
>>since you can't declare things like an adder.
>Huh? Both VHDL and Verilog let you easily declare an adder.
>In VHDL, if you want an adder with inputs A and B, and output C,
>you would write:
> A <= B + C;
>For a complicated system, I find well-written HDL code to be easier to
>understand than schematics.
Now what about carry out? 1's comp adder? Ripple adder or carry skip
adder or
carry lookahead adder? Where is over flow?

> Something that is a single logic equation
>in an HDL might require a dozen gates on a schematic, and would take
>me much longer to unravel than the logic expression would. Back when
>I was designing with TTL, I started with logic equations anyhow, and
>translated that to gates. Back then it made sense, because there wasn't
>software readily available that could do it, and if there had been, it
>probably wouldn't have been as efficient at choosing the implementation
>as I would be doing it by hand. But for complex systems now, it's
>simply not worth the effort to do that by hand. (Though I fully agree
>that it is still vital for hardware engineers to be *trained* how to
>do it.)
>Or I might write:
> A <= B + C when OP = ADD else
> B - C when OP = SUB else
> B sll 1 when OP = SHIFT_LEFT else
> B xor C;
>And those four lines express a simple ALU that would take quite a
>few symbols and signals on schematic. Furthermore, just about everything
>more complex than a logic gate is just a rectangle on the schematic,
>which throws away one of the best potential benefits of a graphical

>And once you get to the point where a single large chip (ASIC, FPGA,
>processor, or whatever) takes up multiple pages to itself, with nothing
>else on the page but off-page connectors, the benefit of schematic
>representation is totally lost.
But one nice thing about some schematic software I was using you can
Zooom in on a
component. I have used FPGA's and found CPLD's to be the 'right size'.

>>Then if you declare
>>something you never know just what the compiler is doing.
>Why? It's not hard to look at the synthesis output.
I do that now, and $%$_at_! when the compiler does something stupid like
ripple carrying my carry look ahead adder terms.
Ben alias Woodlf
Received on Wed Feb 16 2005 - 10:36:20 GMT

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