On Wednesday 16 February 2005 11:36, woodelf wrote:
> Eric Smith wrote:
> >woodelf wrote:
> >> From what little I have seen FPGA's 99% is VHDL and VERLOG
> >>for development. At least with a schematic you could trace out
> >> the logic, I can't make hide nor hair of what the logic is
> >> with the high level logic and you STIIL have to write code at
> >> the bit level since you can't declare things like an adder.
> >
> >Huh? Both VHDL and Verilog let you easily declare an adder.
> >In VHDL, if you want an adder with inputs A and B, and output C,
> >you would write:
> > A <= B + C;
> >
> >For a complicated system, I find well-written HDL code to be easier
> > to understand than schematics.
>
> Now what about carry out? 1's comp adder? Ripple adder or carry skip
> adder or
> carry lookahead adder? Where is over flow?
You can make your own 'adder' block if you really want to. The good
thing about HDLs is that they read more like code than like schematics.
For examble, in VHDL, you'd do something like:
entity myadder is
port (A, B : in STD_LOGIC_VECTOR(15 downto 0);
C : out STD_LOGIC_VECTOR(15 downto 0);
CO : out STD_LOGIC;
CI : in STD_LOGIC);
end myadder;
architecture BEH of myadder is
begin
signal CARRIES : STD_LOGIC_VECTOR(15 downto 0);
C <= (A XOR B) XOR CARRIES;
CARRIES(0) <= CI;
CO <= (A(15) AND B(15))
OR (A(15) AND CARRIES(15))
OR (B(15) AND CARRIES(15);
...
end BEH;
then, somewhere else, you can use:
myadder PORT_MAP( A => INPUT1,
B => INPUT2,
C => OUTPUT,
FROMLASTCARRY => CI,
TONEXTCARRY => CO );
Keep in mind you can usually find the different types of adders in a
'library' somewhere else. Also, this is all VHDL stuff. From what I
understand, Verilog is much less verbose than VHDL is (and more like C
than like ADA).
> >And those four lines express a simple ALU that would take quite a
> >few symbols and signals on schematic. Furthermore, just about
> > everything more complex than a logic gate is just a rectangle on
> > the schematic, which throws away one of the best potential benefits
> > of a graphical representation.
> >
> >
> >
> >And once you get to the point where a single large chip (ASIC, FPGA,
> >processor, or whatever) takes up multiple pages to itself, with
> > nothing else on the page but off-page connectors, the benefit of
> > schematic representation is totally lost.
>
> But one nice thing about some schematic software I was using you can
> Zooom in on a
> component. I have used FPGA's and found CPLD's to be the 'right
> size'.
And, with good HDL CAD software, like what I used in classes at Purdue,
there's a 'schematic capture' package that you can use to connect
together block of stuff, and it outputs an HDL file (typically VHDL or
Verilog). Usually when you're designing something large (like the
32bit RISC CPU with caching, and virtual memory we built in a class I
took), you don't want to concern yourself with gate-level semantics.
But, if you want to, you still can.
> >>Then if you declare
> >>something you never know just what the compiler is doing.
> >
> >Why? It's not hard to look at the synthesis output.
>
> I do that now, and $%$_at_! when the compiler does something stupid like
> ripple carrying my carry look ahead adder terms.
> Ben alias Woodlf
If you care about something like that you can define your own (another
person's) adder like I was showing above, and use that.
Pat
--
Purdue University ITAP/RCS --- http://www.itap.purdue.edu/rcs/
The Computer Refuge --- http://computer-refuge.org
Received on Wed Feb 16 2005 - 11:11:06 GMT